Physical Design Engineer

Physical Design Engineer – ASIC/SoC Development | Senior-Level Position We are seeking an experienced Physical Design Engineer with 10+ years of hands-on ASIC and SoC development experience to join our client's innovative team. This role offers the opportunity to work on cutting-edge System-on-Chip (SoC) projects across multiple emerging technologies, collaborating directly with customers and cross-functional teams to drive successful tape-outs from concept through completion. The ideal candidate will have extensive custom ASIC experience, strong technical communication skills, and a proven track record of multiple tape-outs in small company environments. Key Responsibilities Perform pre-layout static timing analysis (STA) for design feasibility assessment and timing constraint validation Execute chip-level and block-level floorplanning, including strategic pin assignment and power planning Conduct clock specification reviews and implement clock tree synthesis (CTS) optimization Lead placement and routing activities with comprehensive timing optimization and closure Manage physical design synthesis and timing convergence for complex ASIC designs Complete sign-off tasks including RC extraction, static timing analysis, IR-drop analysis, and physical verification (PV) Participate in customer meetings and deliver technical presentations on design progress and solutions Own physical design development from inception through tape-out across the full project lifecycle Required Qualifications Bachelor's degree in Electrical Engineering (BSEE) with 10+ years of hands-on physical design experience; Master's degree (MSEE) strongly preferred Extensive experience in ASIC physical design and SoC development, particularly at advanced process nodes (28nm, 16nm, or smaller) Expert proficiency with physical design tools including ICC2 (IC Compiler II) and/or Cadence Innovus Strong scripting capabilities in Perl, Tcl, and/or Python for design automation Solid understanding of frontend design methodologies and hierarchical layout techniques Working knowledge of power analysis and IR-drop analysis tools such as PrimePower and/or Redhawk Proficiency with static timing analysis using Synopsys PrimeTime or equivalent tools Experience with physical verification tools and debugging complex PV errors (DRC, LVS, antenna violations) Proven track record of multiple successful tape-outs from project inception to completion Previous experience working in small company or startup environments preferred Excellent verbal and written communication skills with ability to interface directly with customers Strong analytical and problem-solving abilities for complex timing and physical design challenges Local candidates strongly preferred Compensation Annual Salary Range: $170,000 - $220,000 USD, commensurate with experience and qualifications Why This Is a Great Opportunity Join a leading custom ASIC and SoC development company at the forefront of advanced semiconductor technology. This position offers: Exposure to a robust pipeline of innovative technology projects for industry-leading companies The opportunity to be a real contributor with significant individual impact and ownership Work on full project lifecycles from initial concept through successful tape-out Collaborative small team environment where your expertise directly influences project outcomes Hands-on technical work with cutting-edge process technologies and emerging applications Direct customer interaction and the chance to shape next-generation SoC solutions Professional growth working on complex, high-performance custom ASIC designs Apply Today If you are a seasoned Physical Design Engineer with deep ASIC/SoC expertise and a passion for challenging technical work, we want to hear from you. Qualified candidates with strong communication skills, custom design experience, and a track record of successful tape-outs are encouraged to apply immediately. Take the next step in your semiconductor career and join a team where your contributions truly matter.